1. Field of the Invention
The present invention generally relates to increasing manufacturing yield of integrated circuit devices and, more particularly, to the formation of various anti-fuse structures in the bulk semiconductor substrate of silicon on insulator (SOI) wafers and similar layered substrates.
2. Description of the Prior Art
The advantages of increased functionality and performance of integrated circuit devices and increased economy of manufacture derived from increased integration density have led to substantial advances in lithography and other manufacturing processes that allow reduction of sizes of transistors, capacitors and other electronic circuit elements and substantial increases in integrated circuit complexity. As integrated circuit complexity increases, however, the likelihood of a malformation of some portion of the integrated circuit during manufacture increases as well. Therefore, it has been a common incident of integrated circuit design to provide for repair of wafers, chips and packages or modules containing the chips at virtually all stages of manufacture so that the expense of processing is not lost.
For example, if a yield or reliability failure is detected after significant wafer processing has been performed, the cost of processing to that point is not lost if performance of the chip can be restored. As other examples currently possible or foreseeable, electrostatic discharge (ESD) protection may be provided during manufacture and disconnected when modules are installed in a system, off-chip driver (OCD) strength can be set based upon load requirements and system failure can be repaired without powering down a system or replacing failed parts.
Such repairs are generally accomplished by the provision of fuses and anti-fuses as potential disconnections and connections that can be made to substitute redundant elements or circuits (e.g. memory cells or partitions) for structures which are defective or of sub-specification performance. Numerous structures and techniques for activating or programming both fuses and anti-fuses are known. In general, more current or voltage must be applied to activate anti-fuses than is required to activate (e.g. destroy/disconnect) a fuse. This fact is becoming more critical at increased integration densities and reduced operating and breakdown voltages due to the potential for damage to other circuit elements since excessive heat voltage and/or current alone or in combination can damage device structures that are becoming more critical with improved performance. Additionally, fuses and anti-fuses require significant chip space (including separations to limit thermal effects) and placement among complex circuits of increased numbers of elements is often difficult.
To obtain highest performance from active devices that may be included in integrated circuits, the use of silicon-on-insulator (SOI) wafer has been generally adopted in recent years. SOI substrates have a relatively thick bulk silicon or other conductive material layer to provide mechanical strength and facilitate handling and packaging and a thin, very high quality monocrystalline silicon active device layer isolated from the bulk silicon by a layer of insulator, generally and oxide.
It is known (but not admitted to be prior art as to the present invention) to allow the structure of some elements formed in the active device layer to extend into the bulk silicon layer. A deep trench capacitor is an example of such a structure. While it is characteristic of SOI structures to be isolated from the bulk layer, such a structure for dynamic memory arrays is advantageous since the capacitor dielectric maintains electrical isolation while allowing the bulk layer to serve as a common electrode for capacitors of the array. While some other structures extending into the bulk silicon layer have been proposed for various purposes including improvement of heat transfer, the basic principle of electrical isolation of the bulk silicon layer from the active device layer must be observed. Further, since the SOI structure is of substantial cost relative to other structure providing lower active device performance, the cost of forming fuses and anti-fuses in terms of the cost of their respective xe2x80x9cfootprintsxe2x80x9d is substantial.
It is therefore an object of the present invention to provide an anti-fuse structure of small footprint size that can be arbitrarily located in an integrated circuit formed on an SOI substrate.
It is another object of the invention to provide an anti-fuse structure having low programming voltage and current and reduced thermal effect on surrounding elements.
It is a further object of the invention to provide an anti-fuse structure which is electrically and thermally isolated from the active device layer of an SOI substrate to avoid compromise of active devices and/or to increase the reliability of an integrated circuit formed therein.
In order to accomplish these and other objects of the invention, an integrated circuit and an anti-fuse structure therefor are provided and formed on a layered substrate including a first semiconductor layer and a second, selectively doped, semiconductor layer insulated therefrom, the anti-fuse comprising a first conductor extending from the first semiconductor layer into the second semiconductor layer and having a programmable element interposed between the first conductor and the second semiconductor layer, a second conductor extending from a surface of the first semiconductor layer to a surface of the second semiconductor layer, and an insulating collar surrounding at least one of the first conductor and said second conductor.
In accordance with another aspect of the invention, a method of making a semiconductor device in a layered substrate comprising first and second semiconductor layers separated by an insulator layer is provided comprising forming a first aperture in the first semiconductor layer and insulator layer to the second insulator layer, forming a second aperture in through the first semiconductor layer and insulator layer extending into the second insulator layer, forming a thin insulator in the second aperture, forming a thick insulator collar in a portion of the first aperture or second aperture, and forming conductors in the first and second apertures.